![]() ![]() Create the library into which all the design units will be compiled.This file sets up the necessary defaults for the Questa tool. Copy the modelsim.ini file that comes with this tutorial into the directory.One time setup for a given directory used for simulation:Įach time you create a directory for simulations you would have to do the following prompt%> add questasim63 OR prompt%> add modelsim.Establishing the Design Environment for compilation This is going to be done using the example of a modified DLX execution block with a 2-stage pipeline. The aim of this tutorial is to understand the basics of working with SystemVerilog in the Questa tool environment. This tool is an advancement over Modelsim in its support for advanced Verification features like coverage databases, coverage driven verification, working with assertions, SystemVerilog constrained-random functionality. The tool provides simulation support for latest standards of SystemC, SystemVerilog, Verilog 2001 standard and VHDL. ![]() QuestaSim is part of the Questa Advanced Functional Verification Platform and is the latest tool in Mentor Graphics tool suite for Functional Verification. 2 Establishing the Design Environment for compilation. ![]()
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